TS-SLD

TS-SLD is the software that automatically converts C language description of a complete cycle Accurate RTL was written using the TOPS Lib.The static scheduling of the module of changed C language description can constitute a high-speed cycle base simulator.

• Automatic conversion to the C language description from RTL (cycle accuracy: 100%)
• high-speed simulation

The so-called development of SoC containing a processor has four stages, a model (Behavior Model) of operation, a RTL model, gate model (Gate Model), and a physical model (Physical Model), in the development process.

By the conventional development technique, the model of SoC containing a processor of operation was described with high-level languages, such as the C language, and the architecture was verified. Then, the RTL model has been described in a hardware description language such as VHDL or Verilog to implement as the LSI. Generally, there is a problem that no longer match the RTL model and the behavior of the initial model. This is because correction enters at the stage of RTL model that it describes the more detailed model of the target LSI.
Ideally, you will need to exactly match the RTL and behavioral models.

TOPS Systems is in default, by implementing the model in RTL simulation speed obtained by the operational model described by language C, offers a solution to solve these problems.

Moreover, in TS-SLD, HW/SW cooperation verification with a system level is enabled taking advantage of the feature of a software model. In contrast, the conventional method using a hardware emulator is faster, more expensive, are targeted only the hardware. Moreover, in RTL, verification of only LSI is a limit.

There are some application methods in TS-SLD. The next figure is the example and is a case where the whole LSI is changed into C model using TS-SLD.

When a RTL model and C model live together in system environment, the cooperation simulation of a RTL model and C model is performed using C model interface (PLI and FLI) of a RTL simulator.

Moreover, when an asynchronous model exists in a system, although TS-SLD is not supporting the asynchronous model, it can use above RTL and the mechanism of the cooperation simulation of C model, and can perform a system-wide simulation.