TOPSTREAM™ Bus

Scalable on-chip bus for multi-core processors
TOPSTREAM ™ Bus protocol is a specification on-chip bus and scalable multi-master multi-slave, and have provided the specifications for the interconnection and management of functional blocks that make up the system-on-chip (SoC) type of multi-core.

Features of TOPSTREAM ™ Bus

• Support up to 8 multi-master multi-slave communication
• High scalability by distributed arbitration
• Throughput of 1 cycle by three-stage pipeline access
• Support for split-transaction
• Support for burst transfer mode
• Support for exclusive control (Lock access)

When you adopt TOPSTREAM ™ Bus hardware IP hardware that implements the protocol (RTL), you can develop without a doubt from the first signal connection only multi-core processors, including the built-in memory and a plurality of processor cores, more than one. TOPSTREAM protocol, by defining a common backbone for the modules that make up the multi-core, we support multi-core design that can be reused.

TOPSTREAM ™ Bus specification was originally developed in 2000, with continuing improvements, to add a protocol specification to provide the necessary functionality to multi-core designs, has led to the current specification.

IP re-use of memory and processor IP core is essential to reduce costs and shorten the development schedule of multi-core processors. TOPSTREAM ™ Bus IP hardware is a standard interface meets the following required conditions, to enable re-use IP.

Scalability
IP re-use of memory and processor IP core, the common variety of multi-core processor that corresponds to the type and number of different conditions, power consumption, performance, memory footprint of IP and the type and number of processor cores connected to standard is required.

Compatibility
TOPSTREAM ™ Bus interface with AMBA APB bus bridge for connecting on-chip peripherals, has a scalability can respond to various conditions.

Event communication
TOPSTREAM ™ Bus interface is equipped with inter-processor communication register in the B bus bridge for connecting on-chip peripherals, has a communication control mechanism between events in the event can accommodate a variety of inter-processor network. (Optional)