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TOPSTREAM™ Platform
TOPSTREAM ™ Platform, the three central challenges for improving the performance of the computer platform of heterogeneous multi-core processors with features of the basic architecture TOPSTREAM ™ to solve (① ILP Wall ② Memory Wall ③ Power Wall) is a (basic design). By using the TOPSTREAM ™ Platform, you can easily design the next generation requirements of a variety of electronic devices (processing speed, power consumption, cost, etc.) a heterogeneous multi-core processor suitable for.
Basic architecture TOPSTRAM ™ is equipped with various mechanisms to solve ILP Wall, Memory Wall is a fundamental challenge in improving performance of three of the microprocessor, the Power Wall.
1. Resolution of ILP[1] Wall
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Processor core clock to run in a complex instruction (instruction / operation number 10 ~)
2. Resolution of Memory Wall
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Processor core (parallel execution of operations and memory access) stream processing that can be
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a large register file (up to 256 general-purpose :32-bit ×, for the data book up to 256 n-bit ×)
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the register bank can be shared between the processor core to inter-processor communication
3. Resolution of Power Wall
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(compensate for the performance by the instruction parallelism by multi-core composite ×) significant reduction in operating frequency
The basic architecture TOPSTRAM ™ to solve the problems of these three has the following features.
＜Features of multi-core processors＞
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The heterogeneous multi-core configuration suitable for the application domain, the microprocessor can be designed with very high energy efficiency (MIPS[2]/mW)of
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The combination of different types of processor cores, possible to design a multi-core processor performance per clock frequency (IPC[3])is high
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With the addition of processor cores, can be easily extended capabilities and performance (scalability is high)
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The share register bank between the processor core, reduce the load on the on-chip bus and memory access
＜Features of the processor core＞
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The stream processing, significantly reduce the degradation in performance due to bus contention
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With the addition of complex instruction, improve the IPC
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The dual instruction set, is easy to define the complex instructions and SIMD type instructions
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By order of the length 16-bit, small footprint
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Compact arithmetic unit corresponding general-purpose instruction, instruction SIMD, complex instruction
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The large register file, reducing the memory reference
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The loop buffer, reducing the (number of cycles) during the processing overhead of loop
＜Features of on-chip bus＞
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(1 line instruction, data lineage 2) extended by the Harvard architecture, a high effective performance
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The three-stage pipeline processing, high throughput
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The data width of 128-bit, high-bandwidth
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The distributed arbitration, multi-core configurations can be changed without changing the logic circuit
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The split-transaction, efficient use of bus
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Access by lock, the exclusive control and priority control is possible
Configuration of the basic architecture TOPSTRAM™
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Configuration element |
Product Specifications |
Feature |
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MC |
32-bit RISC processor core
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basic architecture: Load-Store architecture
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pipeline : 5 stage
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instruction length :16-bit(basic)
32-bit/48-bit(With prefix)
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instructions number: 171 instructions
up to 256 instruction (N-bit data processing)
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operand: 2 operand (Basic)
Operand 3 (special instructions) cc
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Memory space: 4GByte
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MMU: options/li>
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privileged mode: The user / supervisor
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Run mode: branch trace execution / Normal / step
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Low-power consumption modes: Normal / stop / dose
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Interrupt Controller: Built-in type (external interrupt: up to 16)
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Processor bus: 1 instruction lineage (64-bit) ,2 lineage data (32-bit, 128-bit)
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debug controller: each processor bus
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For control systems such as OS
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16-bit instruction length compact
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Up to 256 general-purpose registers
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Built-bit instruction processing system
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Harvard type of expansion bus
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instruction prefetch mechanism
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stream processing mechanism (There is an interlock mechanism)
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Built-in TOPSTREAM ™ S-bus I/F
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ITLB |
Instruction TLB for MC (optional)
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A computer figure table (capacity, number of sets, etc.)
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Choice of a configuration that is suitable for application
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Convert zero cycle address
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DTLB |
TLB data for MC (optional)
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A computer figure table (capacity, number of sets, etc.)
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Choice of a configuration that is suitable for application
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Convert zero cycle address
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MIC |
Instruction cache for the MC (optional)
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A computer figure table (capacity, number of sets, etc.)
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instruction cache bus :64-bit
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Choice of a configuration that is suitable for application
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MDC |
Cache data for the MDC MC (optional)
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A computer figure table (capacity, number of sets, etc.)
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instruction cache bus :32-bit
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Choice of a configuration that is suitable for application
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DPE |
DPE 32-bit RISC type+ n-bit processor core data processing
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basic architecture: Load-Store architecture
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pipeline : 5 stage
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instruction length :16-bit(basic)
32-bit/48-bit(With prefix)
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instructions number: 68 instructions
up to 256 instruction (N-bit data processing)
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operand: 2 operand (Basic)
Operand 3 (special instructions) cc
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general-purpose register bank :32-bit × 16 × 16 banks(maximum)
n-bit × 16 × 16 banks (maximum)
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Memory space: 4GByte
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privileged mode: The user / supervisor
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Run mode: branch trace execution / Normal / step
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Low-power consumption modes: Normal / stop / dose
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Interrupt Controller: Built-in type (external interrupt: up to 16)
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Processor bus: 1 instruction lineage (128-bit) ,2 lineage data (128-bit, 128-bit)
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debug controller: each processor bus
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Can be equipped with up to 8 DPE
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Choice of a configuration that is suitable for application
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high scalability with dual ISA [4]
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instruction prefetch mechanism
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loop buffer mechanism
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stream processing mechanism
(There is an interlock mechanism)
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Built-in TOPSTREAM ™ I-bus I/F
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Built-in TOPSTREAM ™ D-bus I/F
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Built-in TOPSTREAM ™ S-bus I/F
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TOPSTREAM™ I-bus |
On-chip bus for instruction
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Method: Distributed shared bus arbitration type
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Topology: multi-master
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The number of bus-master: the master up to 8
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Arbitration: Round robin adaptive
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Stage: stage 3 (S0: Req, S1: Cmd / Addr, S2: Data)
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Throughput: 1 cycle
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Address :32-bit
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data :128-bit
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Mode: Normal branch destination / (Access 2) Continuous
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instruction of high-bandwidth dedicated bus
(800Mbyte / s @ 50MHz case)
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Ability to transfer instructions / cycle up to 8
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priority access mechanism of the branch destination
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TOPSTREAM™ D-bus |
On-chip bus for date
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Method: Distributed shared bus arbitration type
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Topology: multi-master × multi-slave
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The number of bus-master: the master up to 8
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The number of bus slave: slave up to 8
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Arbitration: Round robin adaptive
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Stage: stage 3 (S0: Req, S1: Cmd / Addr, S2: Data)
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Throughput: 1 cycle
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Address :32-bit
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data :128-bit
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Mode: Normal / Rock
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high-bandwidth data-only bus
(800Mbyte / s @ 50MHz case)
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Adjustable priority by the lock mechanism On-chip bus for date
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TOPSTREAM™ S-bus |
On-chip bus for date
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Method: Distributed shared bus arbitration type
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Topology: multi-master × multi-slave
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The number of bus-master: the master up to 9
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The number of bus slave: slave up to 8
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Arbitration: Round robin adaptive
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Stage: stage 3 (S0: Req, S1: Cmd / Addr, S2: Data)
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Throughput: 1 cycle
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Address :32-bit
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data :128-bit
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Mode: Normal / Rock/ Split
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high-bandwidth data-only bus
(case:800Mbyte/s＠50MHz)
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Adjustable priority by the lock mechanism On-chip bus for date
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Split-transaction
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IM |
For on-chip instruction memory
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Capacity: Configurable
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data width:128-bit
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Bus I/F:TOPSTREAM™ S-bus (Read/Write)TOPSTREAM™ I-bus (Read Only)
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Choice of a configuration that is suitable for application
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between the bus arbitration mechanism
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DM |
On-chip instruction memory for data
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Capacity: Configurable
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data width:128-bit
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Bus I/F:TOPSTREAM™ D-bus (Read/Write) TOPSTREAM™ S-bus (Read/Write)
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Choice of a configuration that is suitable for application
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between the bus arbitration mechanism
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IPU |
On-chip peripheral interfaces
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Bus interface:TOPSTREAM™ S-bus
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Bus Bridge:AMBA APB 32-bit bus
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built-in function: Timer, register inter-processor communication
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I/F to connect to various peripherals/li>
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BC |
External bus controller BC (optional)
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Memory: external I / F: ROM, FLASH, SDRAM, DDR
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Bus I / F Internal: MC (instruction system: MIC, data system: MDC),
TOPSTREAM™ S-bus
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Memory controller
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On-chip bus arbitration
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I / F to connect to various types of memory
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Basic architecture TOPSTRAM ™ performs the control of the entire multi-processor data processing system processor is responsible for various master controller (processor core MC :32-bit RISC) (DPE: 32/64/128/256- is composed of external memory controller and etc. TOPSTREASM ™ Bus, which is unique and proprietary on-chip bus for processor) application-specific domain, such as bit, efficient operation of these processors. Processor can be mounted is a maximum of 8 usually up to eight types as DPE, you can significantly increase the maximum number of processors can be configured in a cluster with eight processors within.
As it can be achieved by combining a processor core suited minimum number of processing performance required for the application, can be integrated in the memory hierarchy and the optimal coupling between processor optimal. The adoption of the basic architecture TOPSTRAM ™, as compared to multi-core processor of traditional ASIC and homogeneous type (semiconductor products for specific customers by hard-wired logic circuits), low power consumption while maintaining performance, more scalable programmable of development (application-specific standard semiconductor products) will be available ASSP.
Also, in addition to the basic architecture TOPSTRAM ™, to adopt a three-dimensional stacked LSI technology, product development and ultra-short-term response to high-mix low-volume will be possible.
The figure shows the configuration of the TOPSTREAM ™ base platform is a multi-core processor design platform based on the basic architecture of TOPSTRAM ™.
※1: Data Processing Engine, the processor core by the generic name of the processor core for data processing on the platform, which is specialized in applications based on the basic architecture of DPE actually is the name of the individual is assigned.
※2:Instructions perform operations in a single instruction number 10, will be executed in one clock basically.
[1] ILP : Instruction Level Parallelism
[2] MIPS : Million Instruction Per Second
[3] IPC : Instruction Per Clock
[4] ISA : Instruction Set Architecture
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