Technical Advisory Board

Tadao Nakamura, Ph.D. (Engineering)

World leading Professor of Computer Architecture and Low-Power Chips.

He is a Professors emeritus of Tohoku University, Professor of Stanford University, Professor of Keio University, and Professor of Imperial College of London. He is IEEE fellow, and received Taylor L. Booth Award from the IEEE Computer Society. He is the Advisory Committee Chair of the IEEE Symposium on Low-Power and High-Speed Chips "COOL Chips".

Tsuneo Tsukahara, Ph.D. (Engineering)

Tsuneo Tsukahara received the B.S. and M.S. degrees in applied physics and the Ph.D. degree in electronic engineering from Tohoku University, Sendai, Japan, in 1979, 1981 and 2001, respectively. In 1981, he joined the Electrical Communications Laboratories, Nippon Telegraph and Telephone Public Corporation (NTT), Tokyo, Japan, where he was involved in device noise analysis and analog integrated circuits design, especially for high-performance A/D and D/A converters, and bipolar / CMOS RF circuits such as a 1-V-operation CMOS transceiver IC. In April 2006, he joined the University of Aizu, Aizu-Wakamatsu City, Fukushima, Japan, where he is currently a Professor in the School of Computer Science and Engineering. His current interests are in CMOS analog/RF circuit design and low-power and high-performance wireless communications LSIs for ubiquitous computing networks and software-defined radios. He published about sixty papers in journals and international conferences, and authored one book entitled “Design of CMOS RF Circuits (Maruzen)” and coauthored six books. He received the 31st Radio Engineering and Electronics Association (REEA) Award entitled “Contributions to Research and Development, and the Practical Use of High Frequency Circuits for Digital Wireless Communications” on Nov. 7, 2017.

Fumio Arakawa, Ph.D. (Engineering)

Fumio Arakawa received his BS and MS degrees in applied physics from the University of Tokyo in 1984 and 1986, respectively, and joined Central Research Laboratory of Hitachi, Ltd. in 1986. His research interests include architecture and micro-architecture of low-power and high-performance microprocessors, and designed a TRON chip in 1986-1992, SuperH RISC engine series processors from 1992. He joined a research PJ of a VLIW processor at HP laboratory in Palo Alto in 1993-1994. He received his Ph.D degree in electrical engineering from the University of Tokyo in 2007. He moved to Renesas Technology Corp. in 2009, which is now Renesas Electronics Corp.

Arakawa was an ITPC member of ISSCC in 2004-2009, a TPC member of A-SSCC in 2005-2011, and the architecture TPC chair of ICD in 2008-2009. He is a committee co-chair of the Cool Chips conference series from 2008, a guest editor of COOL Chips Special Section/Issue of IEEE Micro from 2009, a program committee member of the VLSI Circuits Symposium from 2010, and the chairman of Microprocessor Technical Committee of JEITA from 2009. He is a member of IEEE and IEICE.

Hiroyuki Tomiyama, Ph.D. (Engineering)

He received his Dr.E. degree from Kyushu University in 1999. After he worked at UC Irvine, ISIT Kyushu and Nagoya University, he joined Ritsumeikan University as a full professor in 2010. His research interests include design methodologies for embedded and cyber-physical systems.

Jon Shiell

30+ years in the industry, covering architecture and verification for both processors and systems, Companies have included TI, Sun and HAL.

50+ granted US patents mainly in the processor and system architecture areas.

Extensive knowledge of intellectual property including patent development, evaluation, evidence-of-use development and patent work-around.