For the vision of president Yukoh Matsumoto. "Consumer electronics must introduce scalable reuse of hardware/software from now, which can be realized by heterogeneous multi-processor (multi-core), our company is focusing on the realization of an innovative parallel processing architecture named TOPSTREAM(TM) (Task Oriented Parallel STREAM).

Buisiness Development Member

President and CEO　Ph.D (Information Science) 　Yukoh Matsumoto  

 Founder, a processor architect who created TOPSTREAM(TM) technology

 Yukoh Matsumoto joined TI Japan in April 1986, and engaged to the development of DSP and voice codec LSI. Moved to VM technology in December 1987 and developed a x86 clone processors like VM8600S, VM386SX+. From June 1993 to March 1997, engaged to the development of super-scaler type low-power in TI main office, since March 1997, researched an image codec processor and low power design technology as a researcher in TI Tsukuba R&D center.
December 1997, established TOPS Corporation with Dr. Masatoshi Shima, in charge of technology as a vice president. In Devember 1999, established TOPS Systems Corporation as a president. Awarded Takeda Research Promotion award in 2001. MOT Certification from Tokyo University in 2006, Ph.D Degree in Information Science in 2007 from Tohoku University. 20 years of experience in developing microprocessor like DSP, x86-compatible, super-scaler and multi-core architecture. R&D of High-speed simulator, system level design methodology and HW/SW co-operative design. Application field covers PC, multi-media compression and de-compression, wireless signal processing, encryption system. IEEE computer society, ACM member.

Senior Technical Advisor Ph.D (Engineering)　Tadao Nakamura

An autority of computer architecture and low-power chips.

He is the Chair of the international conference "COOL Chips"　organized by The IEEE (Institute of Electrical and Electronics Engineers) , which focuses on the low power and high speed LSI technology. He is a Professors emeritus of Tohoku University, a Professor of Standord University, a Professor of Keio University since October 2007 and also a Professor of Imperial College of London since autumn 2007. He awarded Taylor L. Booth from The IEEE Computer Society, which is the international top professor of computer science. IEEE fellow.

Business Development Manager C Yoshihisa Shirata

The leading expert of IP business in Japan

He joined TI-Japan as an LSI engineer in April 1986, designed a number of ASIC products as image processing engines for Digital VTR/DSC. In December 1998, he moved to Mentor Graphics Japan as a technical sales for IP core products. The domain of his sales and technical support includes USB IP as well as various IP products. He was promoted to an AR manager of EDA tools for ESL design, HW/SW co-design and assertion verification in December 2005, and became in charge of the business development in the fusion of IP and EDA tools. He felt strong sympathy with the TOPSTREAM™ based on the concept of heterogeneous processing invented by Yukoh Matsumoto, who is the colleague in TI-Japan, since October 2007, became Business Development Manager C of TOPS Systems Corporation in order to give broad advices on marketing and sales activities.

Executive Research Director Ph.D (Engineering) Rimon Ikeno

A researcher of low-power LSI technology.

He received Ph.D degree in semiconductor engineering from University of Tokyo in 1997, and joined Texas Instruments Tsukuba R&D Center, Ltd., where he worked for advanced silicon device technology as Deca-nano Device Project member.
In 1999, he joined Ultra-Low Power DSP project in TI Japan for low power CMOS circuit technology and power management. Then he moved to the DSP development organization in TIJ, and developed C5000 DSP cores for mobile applications using advanced process technologies like 130nm, 90nm, 65nm, and 45nm.
He contributed in many areas like designs of high-performance and low-power data processing modules, introduction of low-power and power-management technologies into DSP designs, collaboration with the advanced process development in TI, and so on.
He was a Senior Member of Technical Staff (SMTS) in Texas Instruments.
In November 2008, he joined TCAD International, Inc. He led an R&D project, "Development of low-power and high-performance sparse matrix processor for high-performance computing", supported by a NEDO donation for venture technology and business development. In this project for hardware/software co-working system, he developed a dedicated micro processor for incomplete LU decomposition of sparse matrix for TCAD and other numerical analysis applications.
In April 2010, he joined TOPS Systems as Executive Research Director in Microprocessor Development Division.
He is a member of IEEE and IEICE, respectively.

 Principal Software Platform Architect　Ph.D (Engineering)　Takeshi Ohkawa

Web site is here.

A researcher of LSI/Software system based on object-oriented manner

Designed a reconfigurable LSI "Flexible Processor" and its Place&Route automation tool "PELOC" during the Ph.D course in Tohoku University, presented the work in an international conference VLSI symposium, and given Ph. D degree of electronics engineering in 2003. The 6th LSI IP design award winner in 2004. Since 2004, he was a researcher in National Institute of Advanced Industrial Science and Technology (AIST) located in Tsukuba, engaged in the realization of ORB engine which is the fusion of distributed object middleware CORBA and LSI using FPGA technology. He completed the NEDO supported research project of "Low-power Object Request Broker (ORB) engine for embedded systems" as a research leader from September 2007 to March 2009.
He started a joint research with TOPS Systems since December 2007, supported TOPS System as a design advisor from November 2008, and joined TOPS Systems as a principal software platform architect in April 2009. He is a member of IPSJ and ACM.

Principal Software Architect Ph.D (Engineering) Takashi Miyazaki

Majored computer science in the graduate school of Keio University.
Mar. 2005: Ph.D degree (engineering)
Apr. 2005 - Oct. 2005: Postdoctral researcher in National Institute of Physiological Sciences.
Nov. 2005 - Jul. 2009: Postdoctral researcher in the University of Tokyo.
Jul. 2009 - Principal software architect in TOPS Systems.
Member of JNNS, JNSS.

Microprocessor Development Division Chief HW/SW System Architect Ph.D (Engineering) Marco Chacin

Marco Chacin is a Member of the IEEE Robotics and Automation Society and Computer Society. He was born in Maracaibo, Venezuela. He received B.S. and M.Sc. degrees in Electronics Engineering and Control Engineering with a concentration in Robotics from Dr. Rafael Belloso Chacin University in 1999 and 2001 respectively.

In 2001, he joined the Dr. Rafael Belloso Chacin University as Professor conducting and directing research as director the Robotics Research Laboratory.

In 2003, he moved to Japan to pursue a Ph.D. degree in Aerospace Engineering (Space Robotics) at Tohoku University under the sponsorship of the Japanese Ministry of Education, Culture, Sports, Science & Technology. His graduation thesis addressed the surface mobility/navigation planning of JAXA's next-generation rover for future asteroid sample return missions.

He attended the IEEE-RAS/IFRR International School of Robotics Science 2005, the Space Generation Congress 2005 and the International Space University Summer Session Program (SSP06).

Upon graduation, he joined the Toyota Motor Corporation to work on the system design and mobility research of the futuristic prototype car i-Unit, and in late 2007 he moved to Cyberdyne Inc. to work on mass-production version of the robot suit HAL, a cyborg-type robot that can expand and improve human physical capabilities.

In April 2010 he joined TOPS Systems as Chief HW/SW System Architect.

Website: MindsPages.net

Summary of Corporation